The increasing operating speeds and computing power of microelectronic devices have given rise to the need for an increase in the complexity and functionality of the semiconductor substrates that are used as the starting substrate in these microelectronic devices. Historically, to maintain low fabrication cost, these semiconductors were built using silicon (Si) substrates. Nevertheless, with increasing speed and functionality requirements, Si substrates become limiting and designers need to use alternative materials that provide improved performance.
Potential alternatives include substrates made from materials such as germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), or gallium nitride (GaN). These alternate materials permit the development of a substrate suitable for a wider range of device types, functionalities, and speed. For example, new technological developments provide the ability to form heterostructures using silicon germanium (SiGe) to further speed up devices by changing the atomic structure of Si to increase electron mobility. These substrates are called strained Si substrates.
A strained Si substrate is generally formed by a first epitaxial growth of a relaxed SiGe layer on bulk Si, and then a second epitaxial growth of a thin (less than about 500 Angstroms) Si layer on the relaxed SiGe layer. Because the lattice constant of relaxed SiGe is different from Si, the thin Si layer becomes “strained,” resulting in enhanced mobilities (and hence improved device speeds) over bulk Si. The percentage of Ge in SiGe, and the method of deposition can have a dramatic effect on the characteristics of the strained Si layer. U.S. Pat. No. 5,442,205, “Semiconductor Heterostructure Devices with Strained Semiconductor Layers,” incorporated herein by reference, demonstrates one such method of producing a strained Si device structure.
A method of epitaxially growing a relaxed SiGe layer on bulk Si is discussed in PCT application WO 01/22482, “Method of Producing Relaxed Silicon Germanium Layers,” incorporated herein by reference. The method includes providing a monocrystalline Si substrate, and then epitaxially growing a graded Si1-xGex layer with increasing Ge concentration at a gradient of less than 25% Ge per micron to a final composition in the range of 0.1≦x≦1, using a source gas of GexHyClz for the Ge component, on the Si substrate at a temperature in excess of 850° C., and then epitaxially growing a semiconductor material on the graded layer. (The terms “SiGe” and “Si1-xGex” are used interchangeably to refer to silicon-germanium alloys.)
Another method of epitaxially growing a relaxed SiGe layer on bulk Si is discussed in a paper entitled, “Low Energy plasma enhanced chemical vapor deposition,” by M. Kummer et. al. (Mat. Sci. & Eng. B89, 2002, pp. 288-95), incorporated herein by reference, in which a method of low-energy plasma-enhanced chemical vapor deposition (LEPECVD) is shown, which allows the formation of a SiGe layer on bulk Si at high growth rates (0.6 micron per minute) and low temperatures (500-750° C.).
SiGe graded layers with low threading dislocation densities (i.e., two-dimensional defects in a single crystal material) are usually thick layers (greater than 1000 Angstroms and often greater than one micron). Consequently, the industry is moving toward chemical vapor deposition (CVD) techniques that allow high growth rates. Nevertheless, to grow a thin (less than 500 Angstroms thick), epitaxial strained Si layer uniformly on the SiGe, a high growth rate process is not optimal. To maintain a high-quality strained Si layer without defects, a low-growth rate, low-temperature (LT) CVD process is preferred. In other words, for developing strained Si substrates, the optimal epitaxial growth process of the first thick SiGe layer on bulk Si is different from the optimal epitaxial growth process of the second thin Si layer.
To grow a high-quality, thin, epitaxial strained Si layer on a graded SiGe layer, the SiGe layer is, ideally, planarized to reduce the surface roughness in the final strained Si substrate. Current methods of chemical mechanical polishing (CMP) are typically used to improve the planarity of surfaces in semiconductor fabrication processes. U.S. Pat. No. 6,107,653, “Controlling Threading Dislocations in Ge on Si Using Graded GeSi Layers and Planarization,” incorporated herein by reference, describes how planarization can be used to improve the quality of SiGe graded layers.
Integrating the development process of strained Si substrates with existing Si-based tools minimizes the re-tooling of fabrication plants. Nevertheless, existing Si fabrication tools generally do not support the process control differences required for the epitaxial growth of the first thick SiGe layer and the second thin Si layer sequentially in the same CVD step. Additionally, a planarization step may be inserted between the thick SiGe layer deposition and the thin Si layer deposition to ensure that the resulting substrate has good surface morphology.
One challenge to the manufacturability of semiconductor devices that include strained layers is that one or more high temperature processing steps are typically employed after the addition of the strained material. This can cause intermixing of the strained layer and adjacent material. This intermixing is generally referred to as interdiffusion, and it can be described by well-known diffusion theory (e.g., Fick's laws). One example of interdiffusion is found in a field effect transistor (“FET”) where a strained layer is used as the channel. In this example, one or more impurities (e.g., dopants) are implanted after addition of the strained layer. If implantation is followed by a moderately high temperature step (e.g., a drive-in or anneal step), there can be rampant interdiffusion of the channel by the implant impurity due to the presence of implant damage and excess point defects in the strained layer. A result is that the impurity is present in the strained layer. Stated differently, the impurity profile (i.e., a gradient describing the impurity concentration as a function of location in the overall semiconductor or device) has a non-zero value in the strained layer. Presence of one or more impurities in the strained layer can, at certain concentrations, degrade overall device performance.
From the foregoing, it is apparent that there is still a need for a way to produce semiconductor structures by rapidly growing a thick SiGe layer followed by growing a thin, high-quality, strained Si layer. Further, it is desirable to accomplish this with a process tool that integrates the fabrication steps and allows for planarizing the SiGe layer. It is advantageous for the resulting structures to exhibit minimal incursion of one or more impurity species into the strained layer.